Modern integrated circuits, including modern microprocessors, utilize stacked layers of a conductive material to provide electrical connectivity between various devices formed in a base layer of semiconductor materials. These conductive layers, which are electrically isolated by insulator layers formed between each conductive layer, carry signals within and between the devices during operation of the integrated circuit. Stacked conductive layers are used to interconnect the devices, instead of a single conductive layer, in order to minimize the footprint of the integrated circuit. By making integrated circuits with smaller footprints, complex electronic equipment can be employed in many applications where space is critical, such as in aircraft; space vehicles; and consumer products such as computers, watches, calculators, automobiles, telephones, televisions, and appliances. In addition, reducing the footprint of an integrated circuit minimizes the separation of the various devices and correspondingly minimizes the time delay of signals transferred between the devices.
However, this stacking of conductive layers also makes the debugging of an integrated circuit and the implementation of prototype design changes to an integrated circuit a more difficult and time consuming process. To implement physical changes to an integrated circuit required by such debugging or design changes, one typically (1) modifies the masks for the semiconductor layer, the conductive layers, or both the semiconductor and conductive layers or (2) attempts to utilize existing conductive lines and devices in the circuit. As used in this document, a "device" refers to a plurality of CMOS (complimentary metal-oxide-silicon) transistors interconnected by electrically conductive lines in the conventional manner to form inverters, AND gates, OR gates, NAND gates, NOR gates, latches, or other conventional integrated circuit devices.
Modifying masks and remanufacturing the integrated circuit may take as long as eight weeks or more for an integrated circuit as complex as a microprocessor. During this time, an error which one is attempting to debug may prevent or greatly reduce debugging efforts on the rest of the microprocessor.
Attempting to utilize existing conductive lines and devices in the circuit is also a time consuming process. First, one must select the device to be utilized. Next, one must form the necessary interconnections between devices. Such interconnections are typically formed using conventional focused ion beam (FIB) equipment, such as the IDS P2X ProbePoint Extension sold by Schlumberger. The FIB, or similar equipment used to make these interconnections, is capable of removing conductive and/or insulator layers of a circuit to create a via providing access to a particular device or conductive line; cutting an existing conductive line in a circuit; and depositing conductive materials such as metals and metal alloys within vias and on the top insulator layer of a circuit.
FIG. 15a provides a first example of such a conventional interconnection in which a "problem" inverter 400, having an input 402 and an output 404, is replaced with a "cannibalized" inverter 406, having an input 408 and an output 410. First, a FIB is used to cut through the conductive and insulator layers (not shown) of the microprocessor to create vias 412 providing access to input lines 402 and 408 and output lines 404 and 410. Next, a FIB is used to deposit a conductive line 414 in vias 412 and on the top insulator layer (not shown) of the microprocessor to interconnect input line 402 with input line 408. Similarly, a FIB is used to deposit a conductive line in vias 412 and on the top insulator layer (not shown) of the microprocessor to interconnect output line 404 with output line 410. Finally, a FIB is used to cut output line 404 to create a discontinuity 418, to cut input line 408 to create a discontinuity 420, and to cut output line 410 to create a discontinuity 422. As part of the selection of the device to be cannibalized, one should verify that the cannibalized device has no effect on the problem logic being debugged, the circuit logic to be modified, or other circuit logic which is dependent on the cannibalized device and is being debugged concurrently.
FIG. 15b provides a second example of such a conventional interconnection between a NAND gate 500, having an input 502, an input 504, and an output 506, and a second NAND gate 508, having an output 510. First, a FIB is used to cut through the conductive and insulator layers (not shown) of the microprocessor to create vias 512 providing access to input line 504 and output line 510. Next, a FIB is used to deposit a conductive line 514 in vias 412 and on the top insulator layer (not shown) of the microprocessor to interconnect input line 504 with output line 510. Finally, a FIB is used to cut input line 504 to create a discontinuity 516.
Creating such conventional interconnections with a FIB is a very time consuming process. Using a FIB to cut a via through a single conductive layer, and its corresponding insulator layer, typically requires on the order of one-half hour to one hour. In addition, using a FIB to deposit a conductive line having a length of 500 .mu.m on the top insulator layer of a microprocessor typically takes on the order of five hours. One should note that in an integrated circuit as complex as a microprocessor, many more than the minimum of two FIB vias and one FIB conductive line may be required to form each of the above-described interconnections due to the complexity of the routing of the conductive layers.
Furthermore, when performing such conventional interconnections with a FIB, one often faces several additional problems other than the time consuming nature of the process, as described above. First, a FIB can only reliably deposit a conductive line having a length of no more than 500 .mu.m to 1000 .mu.m. Such limited FIB line length is due to the high resistance of FIB lines. Second, FIB lines are less reliable than conductive lines created by conventional masking due to a higher frequency of voids or discontinuities in FIB lines. Third, in many instances, such interconnections may not be possible due to the particular layout of the integrated circuit. For example, in many layouts, it is impossible to reliably create the FIB vias for the necessary interconnections due to existing conductive lines overlying a desired point in the circuit. As another example, some layouts may require a FIB line having a length greater than 1000 .mu.m, and therefore it is not possible to create the necessary interconnections using a FIB. As a further example, some layouts may require a FIB line having a length greater than 500 .mu.m, and therefore it is not possible to create the necessary interconnections using a FIB without a high possibility of reliability problems for the FIB line. In these situations, modifying the masks and remanufacturing the circuit may be the most practical option.
One should also note that it is conventional to include "spare devices" in modern microprocessors, as space on the semiconductor surface permits. As used in this document, a "spare device" refers to a device having no function in a routed integrated circuit as originally designed. However, the existence of spare devices may not always facilitate the above-described conventional interconnection process. For example, a spare device may be located on the circuit so as to require a FIB line of greater than 500 .mu.m to 1000 .mu.m. As another example, it may be impossible to create a FIB via to the input or output lines of a spare device due to existing conductive lines overlying the input or output lines. Therefore, a need exists in the industry to provide a technique of reprogramming an integrated circuit which requires a minimum amount of time and which does not suffer from the above-described limitations and reliability problems.
It is therefore an object of the present invention to provide an integrated circuit which can be reliably reprogrammed to debug errors or implement prototype design changes without requiring modification of masks and remanufacturing of the circuit.
It is a further object of the present invention to provide such an integrated circuit which can be reprogrammed in a minimum amount of time.
It is a further object of the present invention to provide such an integrated circuit in which conductive interconnections made by a FIB are no more than 500 .mu.m in length.
Still other objects and advantages of the present invention will become apparent to those of ordinary skill in the art having reference to the following specification together with its drawings.